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ChipChat is a natural language interface that lets users describe a circuit and instantly gain access to an end-to-end chip development pipeline. From prompt ideation to Verilog code to the final manufacturing file, our goal is to make hardware design more intuitive, accessible, and fast.

🏆 Winner - UC Berkeley AI Hackathon 2025

Grand Prize winner in the Productivity and Dev Tools Track, demonstrating the potential of AI-driven hardware design tools.

Demo Video

Watch ChipChat in action as it transforms natural language descriptions into complete circuit designs and manufacturing files.

The Challenge

Designing hardware is hard. Engineers spend countless hours writing Verilog and refining circuit layouts, while students face a steep learning curve with abstract logic gate diagrams. As undergraduates, we've struggled to actively engage with circuits and learn through hands-on experimentation.

"We've also seen PhD students spend years iterating on chip designs through long cycles of development and testing."

Our Solution

ChipChat takes multimodal user inputs (as written prompts or image queries) for a circuit description and provides the complete Verilog code, comprehensive circuit design diagram, and full pipeline. Users can bring their circuits to life with interactive inputs and navigate through every component to understand the details.

💬

Natural Language Interface

Describe circuits in simple terms or upload hand-drawn sketches - no complex syntax required

End-to-End Pipeline

From Verilog generation to final GDS manufacturing files, complete the entire chip development process

🎯

Interactive Visualization

Pan around and explore circuit structures with HTML and SVG-based visualizations

🤖

AI Circuit Assistant

Ask questions about code or diagrams and receive accurate, real-time answers

Technical Implementation

Complete Hardware Development Pipeline

AI & Processing

  • Gemini + Letta integration for natural language processing
  • Multimodal input handling (text + image queries)
  • Context-aware Verilog code generation

Hardware Tools

  • Yosys for Verilog synthesis and optimization
  • OpenLane for chip layout and routing
  • DigitalJS for interactive circuit visualization

System Architecture

📝

RTL Design (Verilog)

Write high-level behavioral code that defines how the circuit should function logically

🔧

Synthesis

Translate behavioral Verilog into a gate-level netlist using standard logic cells

📍

Place and Route (DEF)

Determine physical locations of each gate and route interconnections on chip layout

🏭

Layout Generation (GDS)

Create final mask layout file containing all geometric layers needed for chip fabrication

Technical Stack

Frontend

ReactTypeScriptViteHTMLCSSSVG

Backend & AI

Node.jsGemini AILettaPythonBash

Hardware Tools

YosysOpenLaneDigitalJSVerilogVHDL

Deployment

VercelDockerRenderGit

Key Achievements

We're incredibly proud of the pipeline we created in just 24 hours. We've consistently struggled with circuit design in our research, classes, and personal projects. To have a resource that could help us grow as well as thousands of others aspiring to learn the nuances of circuit design is a tremendous feeling.

24-Hour Development

Built a complete end-to-end circuit design platform from scratch in a single day

Educational Impact

Making hardware design accessible to students and engineers worldwide

Future Vision

Within only a day, we've been able to create an end-to-end circuit design platform that's not only interactive and educational, but also provides key files for fabrication. We strive to develop a proprietary model to help understand how to build full-scale analog and digital circuits, and eventually complex hardware such as CPUs and GPUs.

"These applications could redefine industry and research, where billions of dollars are spent on chip performance and efficiency."